
2000 Microchip Technology Inc.
Preliminary
DS41124C-page 19
PIC16C745/765
Bank 2
100h
INDF(3)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
101h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
102h
PCL(3)
Program Counter's (PC) Least Significant Byte
0000 0000
103h
STATUS(3)
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
104h
FSR(3)
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
105h
—
Unimplemented
—
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
107h
—
Unimplemented
—
108h
—
Unimplemented
—
109h
—
Unimplemented
—
10Ah
PCLATH(1,3)
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh
INTCON(3)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Ch-
11Fh
—
Unimplemented
—
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2:
Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3:
These registers can be addressed from any bank.
4:
The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
745cov.book Page 19 Wednesday, August 2, 2000 8:24 AM